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| TDA9885; TDA9886 I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators Rev. 03 -- 16 December 2008 Product data sheet 1. General description The TDA9885 is an alignment-free multistandard (PAL and NTSC) vision and sound IF signal Phase-Locked Loop (PLL) demodulator for negative modulation only and FM processing. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation, including sound AM and FM processing. 2. Features I 5 V supply voltage I Gain controlled wideband Vision Intermediate Frequency (VIF) amplifier, AC-coupled I Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics, and excellent pulse response I Gated phase detector for L and L-accent standard I Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus I Digital acquisition help, VIF frequencies of 33.4 MHz, 33.9 MHz, 38.0 MHz, 38.9 MHz, 45.75 MHz and 58.75 MHz I 4 MHz reference frequency input: signal from PLL tuning system or operating as crystal oscillator I VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals I Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter, AFC bits readable via I2C-bus I TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer I Fully integrated sound carrier trap for 4.5 MHz, 5.5 MHz, 6.0 MHz and 6.5 MHz, controlled by FM-PLL oscillator I Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode, PLL controlled I SIF AGC for gain controlled SIF amplifier, single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus I AM demodulator without extra reference circuit I Alignment-free selective FM-PLL demodulator with high linearity and low noise NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators I Four selectable I2C-bus addresses I I2C-bus control for all functions I I2C-bus transceiver with pin programmable Module ADdress (MAD) 3. Applications I TV, VTR, PC, and STB applications 4. Quick reference data Table 1. Symbol VP IP P Video part Vi(VIF)(rms) GVIF(cr) fVIF VIF input voltage sensitivity (RMS value) control range VIF gain vision carrier operating frequencies -1 dB video at output see Figure 9 see Table 13 60 fVIF Vo(v)(p-p) VIF frequency window of digital acquisition help video output voltage (peak-to-peak value) related to fVIF; see Figure 12 see Figure 7 normal mode (sound carrier trap active) and sound carrier on trap bypass mode and sound carrier off Gdif differential gain [2] [3] Quick reference data Parameter supply voltage supply current time constant (R x C) for network at pin VP for applications without I2C-bus Conditions [1] Min 4.5 52 1.2 Typ 5.0 63 - Max 5.5 70 - Unit V mA s 60 66 33.4 33.9 38.0 38.9 45.75 58.75 2.3 100 - V dB MHz MHz MHz MHz MHz MHz MHz - 1.7 0.95 [2] 2.0 1.10 2 6 4.05 5.00 5.50 5.95 36 36 2.3 1.25 5 7 4 - V V % % deg MHz MHz MHz MHz MHz dB dB "ITU-T J.63 line 330" B/G standard L standard dif Bv(-1dB) differential phase -1 dB video bandwidth "ITU-T J.63 line 330" trap bypass mode and sound carrier off; AC load: CL < 20 pF, RL > 1 k ftrap = 4.5 MHz ftrap = 5.5 MHz ftrap = 6.0 MHz ftrap = 6.5 MHz f = 4.5 MHz f = 5.5 MHz 5 3.95 4.90 5.40 5.50 30 30 Bv(-3dB)(trap) -3 dB video bandwidth including sound carrier trap [4] [4] [4] [4] SC1 attenuation at first sound carrier TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 2 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 1. Symbol S/NW Quick reference data ...continued Parameter weighted signal-to-noise ratio Conditions unified weighting filter ("ITU-T J.61"); see Figure 13 fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 8 definition: IAFC / fVIF 27 kHz FM deviation; 50 s de-emphasis 25 kHz FM deviation; 50 s de-emphasis 54 % AM modulation without de-emphasis; measured with FM-PLL filter of Figure 26 black picture; see Figure 21 in accordance with "ITU-R BS.468-4" referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % see Figure 8 fripple = 70 Hz; see Figure 8 [5] Min 56 20 Typ 59 25 Max - Unit dB dB PSRRCVBS power supply ripple rejection on pin CVBS AFCstps Audio part Vo(AF)(rms) THD BAF(-3dB) S/NW(AF) AM(sup) AF output voltage (RMS value) total harmonic distortion -3 dB AF bandwidth weighted signal-to-noise ratio of audio signal AM suppression of FM demodulator power supply ripple rejection power supply ripple rejection AFC control steepness 0.85 430 80 50 45 40 1.05 540 0.15 0.5 100 56 50 46 1.25 650 0.50 1.0 - A/kHz mV % % kHz dB dB dB PSRRAM PSRRFM Vo(intc)(rms) 20 14 90 90 [6] 26 20 140 140 75 180 180 - dB dB mV mV mV IF intercarrier output level QSS mode; SC1; SC2 off (RMS value) L standard; without modulation intercarrier mode; PC / SC1 = 20 dB; SC2 off - Reference frequency input; pin REF fref Vref(rms) reference signal frequency reference signal voltage (RMS value) operation as input terminal [7] 80 4 - 400 MHz mV [1] [2] [3] [4] [5] Values of video and sound parameters can be decreased at VP = 4.5 V. The sound carrier trap can be bypassed by switching the I2C-bus. In this way the full composite video spectrum appears at pin CVBS. The amplitude is 1.1 V (p-p). Condition: luminance range (5 steps) from 0 % to 100 %. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps (see Figure 15 to Figure 20; H (s) is the absolute value of transfer function). S/N is the ratio of black-to-white amplitude to the noise voltage (RMS value measured on pin CVBS and tested at video black level, `quiet line'). Noise analyzer settings: B = 5 MHz, 200 kHz high-pass and sound carrier trap on. In case of S/NW weighted in accordance with "ITU-T J.61". Measurements taken for B/G standard. The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: V o(intc)(rms) = 1.1 x --------- x 10 V and r = ----- x --------------- ( dB ) + 6 dB 3 dB , where: --------- is the 20 V [6] 1 22 r 1 V i ( SC ) i ( PC ) 1 22 V i ( SC ) correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 in dB, 6 dB is the correction term V i ( PC ) of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 3 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators [7] Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. 5. Ordering information Table 2. Ordering information Package Name TDA9885T/V3 TDA9885TS/V3 TDA9885HN/V3 TDA9886T/V4 TDA9886TS/V4 TDA9886HN/V4 TDA9885T/V5 TDA9885TS/V5 TDA9885HN/V5 TDA9886T/V5 TDA9886TS/V5 TDA9886HN/V5 SO24 SSOP24 HVQFN32 SO24 SSOP24 HVQFN32 SO24 SSOP24 HVQFN32 SO24 SSOP24 HVQFN32 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Version SOT137-1 SOT340-1 SOT617-3 SOT137-1 SOT340-1 SOT617-3 SOT137-1 SOT340-1 SOT617-3 SOT137-1 SOT340-1 SOT617-3 Type number TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 4 of 56 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 03 -- 16 December 2008 (c) NXP B.V. 2008. All rights reserved. TDA9885_TDA9886_3 6. Block diagram NXP Semiconductors CVAGC(pos) VIF-PLL filter VAGC(1) 16 (17) CBL external reference signal or 4 MHz crystal TOP 9 (8) TAGC 14 (15) CAGC(neg) VPLL 19 (21) REF 15 (16) AFC 21 (23) TUNER AGC VIF AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR VIF2 VIF1 2 (31) 1 (30) VIF PLL I2C-bus controlled multistandard alignment-free IF-PLL demodulators SOUND CARRIER TRAPS 4.5 MHz to 6.5 MHz (18) 17 CVBS video output: 2 V (p-p) [1.1 V (p-p) without trap] TDA9885 TDA9886 (7) 8 SIF2 SIF1 24 (27) 23 (26) SINGLE REFERENCE QSS MIXER INTERCARRIER MIXER AND AM DEMODULATOR MAD (4) 6 SUPPLY SIF AGC CAGC AUD DEEM AUDIO PROCESSING AND SWITCHES audio output (3) 5 de-emphasis network AFD CAF OUTPUT PORTS I2C-BUS TRANSCEIVER NARROWBAND FM-PLL DEMODULATOR TDA9885; TDA9886 20 (22) VP 18 (20) AGND (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) 13 n.c. 3 (1) OP1 22 (24) 11 (10) OP2 SCL 10 (9) SDA 7 (5) DGND 12 (11) SIOMAD 4 (2) FMPLL 008aaa174 sound intercarrier output and MAD select FM-PLL filter Pin numbers for TDA9885HN and TDA9886HN in parentheses. (1) Not connected for TDA9885 5 of 56 Fig 1. Block diagram of TDA9885; TDA9886 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 7. Pinning information 7.1 Pinning VIF1 VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP 1 2 3 4 5 6 7 8 9 24 SIF2 23 SIF1 22 OP2 21 AFC 20 VP 19 VPLL 18 AGND 17 CVBS 16 VAGC(1) 15 REF 14 TAGC 13 n.c. 001aai897 VIF1 VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP 1 2 3 4 5 6 7 8 9 24 SIF2 23 SIF1 22 OP2 21 AFC 20 VP 19 VPLL 18 AGND 17 CVBS 16 VAGC(1) 15 REF 14 TAGC 13 n.c. 001aai898 TDA9885T TDA9886T TDA9885TS TDA9886TS SDA 10 SCL 11 SIOMAD 12 SDA 10 SCL 11 SIOMAD 12 (1) Not connected for TDA9885T (1) Not connected for TDA9885TS Fig 2. Pin configuration for SO24 Fig 3. Pin configuration for SSOP24 31 VIF2 30 VIF1 27 SIF2 26 SIF1 32 n.c. 29 n.c. 28 n.c. terminal 1 index area OP1 FMPLL DEEM AFD DGND n.c. AUD TOP 1 2 3 4 5 6 7 8 25 n.c. 24 OP2 23 AFC 22 VP 21 VPLL 20 AGND 19 n.c. 18 CVBS 17 VAGC(1) REF 16 001aai899 TDA9885HN TDA9886HN SCL 10 SIOMAD 11 n.c. 12 n.c. 13 n.c. 14 Transparent top view (1) Not connected for TDA9885HN Fig 4. Pin configuration for HVQFN32 TDA9885_TDA9886_3 TAGC 15 SDA 9 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 6 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 7.2 Pin description Table 3. Symbol Pin description Pin TDA9885T TDA9886T TDA9885HN TDA9886HN TDA9885TS TDA9886TS VIF1 VIF2 n.c. OP1 FMPLL DEEM AFD DGND n.c. AUD TOP SDA SCL n.c. n.c. n.c. TAGC REF VAGC n.c. CVBS n.c. AGND VPLL VP AFC OP2 n.c. SIF1 SIF2 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VIF differential input 1 VIF differential input 2 not connected output port 1; open-collector FM PLL for loop filter de-emphasis output for capacitor AF DC-decoupling capacitor digital ground not connected audio output tuner AGC TOP for resistor adjustment I2C-bus data input and output I2C-bus clock input sound intercarrier output and MAD select with resistor not connected not connected not connected tuner AGC output 4 MHz crystal or reference signal input VIF AGC for capacitor not connected composite video output not connected analog ground VIF PLL for loop filter supply voltage AFC output output port 2; open-collector not connected SIF differential input 1 and MAD select with resistor SIF differential input 2 and MAD select with resistor not connected not connected Description SIOMAD 12 TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 7 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 8. Functional description Figure 1 shows the simplified block diagram of the device which comprises the following functional blocks: * * * * * * * * * * * * * * * * VIF amplifier Tuner AGC and VIF AGC VIF-AGC detector Frequency Phase-Locked Loop (FPLL) detector VCO and divider AFC and digital acquisition help Video demodulator and amplifier Sound carrier trap SIF amplifier SIF-AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant Internal voltage stabilizer I2C-bus transceiver and MAD 8.1 VIF amplifier The VIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration and collector resistor variation. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF. 8.2 Tuner AGC and VIF AGC This block adapts the voltage, generated at the VIF-AGC detector, to the internal signal processing at the VIF amplifier and performs the tuner AGC control current generation. The onset of the tuner AGC control current generation can be set either via the I2C-bus (see Table 12) or optionally by a potentiometer at pin TOP (in case that the I2C-bus information cannot be stored, related to the device). The presence of a potentiometer is automatically detected and the I2C-bus setting is disabled. Furthermore, derived from the AGC detector voltage, a comparator is used to detect if the corresponding VIF input voltage is higher than 200 V. This information can be read out via the I2C-bus (bit VIFLEV = 1). TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 8 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 8.3 VIF-AGC detector Gain control is performed by sync level detection (negative modulation) or peak white detection (positive modulation). For negative modulation, the sync level voltage is stored at an integrated capacitor by means of a fast peak detector. This voltage is compared with a reference voltage (nominal sync level) by a comparator which charges or discharges the integrated AGC capacitor for providing of the required VIF gain. The time constants for decreasing or increasing the gain are nearly equal and the total AGC reaction time is fast to cope with `aeroplane fluttering'. For positive modulation, the white peak level voltage is compared with a reference voltage (nominal white level) by a comparator which charges (fast) or discharges (slow) the external AGC capacitor directly for providing the required VIF gain. The need of a very long time constant for VIF gain increase is due to peak white level may appear only once in a field. In order to reduce this time constant, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step controlled by the detected actual black level voltage. The threshold level for fast mode AGC is typically -6 dB video amplitude. The fast mode state is also transferred to the SIF-AGC detector for speed-up. In case of missing peak white pulses, the VIF gain increase is limited to typically +3 dB by comparing the detected actual black level voltage with a corresponding reference voltage. 8.4 FPLL detector The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier for removing the video AM. During acquisition the frequency detector produces a current proportional to the frequency difference between the VIF and the VCO signals. After frequency lock-in the phase detector produces a current proportional to the phase difference between the VIF and the VCO signals. The currents from the frequency and phase detectors are charged into the loop filter which controls the VIF VCO and locks it to the frequency and phase of the VIF carrier. For a positive modulated VIF signal, the charging currents are optional gated by the composite sync in order to avoid signal distortion in case of overmodulation. The gating depth is switchable via the I2C-bus. 8.5 VCO and divider The VCO of the VIF FPLL operates as an integrated low radiation relaxation oscillator at double the picture carrier frequency. The control voltage, required to tune the VCO to double the picture carrier frequency, is generated at the loop filter by the frequency phase detector. The possible frequency range is 50 MHz to 140 MHz (typical value). The oscillator frequency is divided-by-two to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the frequency, for use in the FPLL detectors, the video demodulator and the intercarrier mixer. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 9 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 8.6 AFC and digital acquisition help Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency range. To prevent false locking of the PLLs and with respect to the catching range, the digital acquisition help provides an individual control, until the frequency of the VCO is within the preselected standard dependent lock-in window of the PLL. The in-window and out-window control at the FM PLL is additionally used to mute the audio stage (if auto mute is selected via the I2C-bus). The working principle of the digital acquisition help is as follows. The PLL VCO output is connected to a down counter which has a predefined start value (standard dependent). The VCO frequency clocks the down counter for a fixed gate time. Thereafter, the down counter stop value is analyzed. In case the stop value is higher (lower) than the expected value range, the VCO frequency is lower (higher) than the wanted lock-in window frequency range. A positive (negative) control current is injected into the PLL loop filter and consequently the VCO frequency is increased (decreased) and a new counting cycle starts. The gate time as well as the control logic of the acquisition help circuit is dependent on the precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as well as connecting this input via a serial capacitor to an external reference frequency, e.g. the tuning system oscillator. The AFC signal is derived from the corresponding down counter stop value after a counting cycle. The last four bits are latched and can be read out via the I2C-bus (see Table 8). Also the digital-to-analog converted value is given as current at pin AFC. 8.7 Video demodulator and amplifier The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The VIF signal is multiplied with the `in phase' signal of the VIF-PLL VCO. The demodulator output signal is fed into the video preamplifier via a level shift stage with integrated low-pass filter to achieve carrier harmonics attenuation. The output signal of the preamplifier is fed to the VIF-AGC detector (see Section 8.3) and in the sound trap mode also fed internally to the integrated sound carrier trap (see Section 8.8). The differential trap output signal is converted to a single-ended signal and amplified by the following post-amplifier. The video output level at pin CVBS is 2 V (p-p). In the trap bypass mode the output signal of the preamplifier is fed directly through the post-amplifier to pin CVBS. The output video level is 1.1 V (p-p) for using an external sound trap with 10 % overall loss. Noise clipping is provided in both cases. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 10 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 8.8 Sound carrier trap The sound trap is constructed of three separate traps to realize sufficient suppression of the first and second sound carriers. For frequency control of the sound trap additionally a reference low-pass filter and a phase detector are built in. A sound carrier reference signal is fed into the reference low-pass filter and is shifted by nominal 90 degrees. The phase detector compares the original reference signal with the signal shifted by the reference filter and produces a DC voltage by charging or discharging an integrated capacitor with a current proportional to the phase difference between both signals, respectively to the frequency error of the integrated filters. The DC voltage controls the frequency position of the reference filter and the sound trap. So the accurate frequency position for the different standards is set by the sound carrier reference signal. 8.9 SIF amplifier The SIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration and collector resistor variation. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF. 8.10 SIF-AGC detector SIF gain control is performed by detection and controlling to a reference value of the DC component of the AM demodulator output signal. This DC signal corresponds directly to the SIF voltage at the output of the SIF amplifier so that a constant SIF signal is supplied to the AM demodulator and to the single reference QSS mixer. By switching the gain of the input amplifier of the SIF-AGC detector via the I2C-bus, the internal SIF level for FM sound is 5.5 dB lower than for AM sound. This is to adapt the SIF-AGC characteristic to the VIF-AGC characteristic. The adaption is ideal for a picture-to-sound FM carrier ratio of 13 dB. Via a comparator, the integrated AGC capacitor is charged or discharged for providing the required SIF gain. Due to AM sound, the AGC reaction time is slow (fc < 20 Hz for the closed AGC loop). For reducing this AM sound time constant in the event of a decreasing IF amplitude step, the charge/discharge current of the AGC capacitor is increased (fast mode) when the VIF-AGC detector (at positive modulation mode) operates in the fast mode too. An additional circuit (threshold approximately 7 dB) ensures a very fast gain reduction for a large increasing IF amplitude step. 8.11 Single reference QSS mixer With the present system a high performance Hi-Fi stereo sound processing can be achieved. For a simplified application without a SIF SAW filter, the single reference QSS mixer can be switched to the intercarrier mode via the I2C-bus. The single reference QSS mixer generates the 2nd FM TV sound intercarrier signal. It is realized by a linear multiplier which multiplies the SIF amplifier output signal and the VIF-PLL VCO signal (90 degrees output) which is locked to the picture carrier. In this way the QSS mixer operates as a quadrature mixer in the intercarrier mode and provides suppression of the low frequency video signals. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 11 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators The QSS mixer output signal is fed internally via a high-pass and low-pass combination to the FM demodulator as well as via an operational amplifier to the intercarrier output pin SIOMAD. 8.12 AM demodulator The amplitude modulated SIF amplifier output signal is fed both to a two-stage limiting amplifier that removes the AM and to a linear multiplier. The result of the multiplication of the SIF signal with the limiter output signal is AM demodulation (passive synchronous demodulator). The demodulator output signal is fed via a low-pass filter that attenuates the carrier harmonics and through the input amplifier of the SIF-AGC detector to the audio amplifier. 8.13 FM demodulator and acquisition help The narrowband FM-PLL detector consists of: * Gain controlled FM amplifier and AGC detector * Narrowband PLL The 2nd SIF signal from the intercarrier mixer is fed to the input of an AC-coupled gain controlled amplifier with two stages. The gain controlled output signal is fed to the phase detector of the narrowband FM PLL (FM demodulator). For good selectivity and robustness against disturbance caused by the video signal, a high linearity of the gain controlled FM amplifier and of the phase detector as well as a constant signal level are required. The gain control is done by means of an `in phase' demodulator for the 2nd SIF signal (from the output of the FM amplifier). The demodulation output is fed into a comparator for charging or discharging the integrated AGC capacitor. This leads to a mean value AGC loop to control the gain of the FM amplifier. The FM demodulator is realized as a narrowband PLL with an external loop filter, which provides the necessary selectivity (bandwidth approximately 100 kHz). To achieve good selectivity, a linear phase detector and a constant input level are required. The gain controlled intercarrier signal from the FM amplifier is fed to the phase detector. The phase detector controls via the loop filter the integrated low radiation relaxation oscillator. The designed frequency range is from 4 MHz to 7 MHz. The VCO within the FM PLL is phase-locked to the incoming 2nd SIF signal, which is frequency modulated. As well as this, the VCO control voltage is superimposed by the AF voltage. Therefore, the VCO tracks with the FM of the 2nd SIF signal. So, the AF voltage is present at the loop filter and is typically 5 mV (RMS) for 27 kHz FM deviation. This AF signal is fed via a buffer to the audio amplifier. The correct locking of the PLL is supported by the digital acquisition help circuit (see Section 8.6). 8.14 Audio amplifier and mute time constant The audio amplifier consists of two parts: * AF preamplifier * AF output amplifier TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 12 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators The AF preamplifier used for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator is 5 mV (RMS) for a frequency deviation of 27 kHz and is amplified by 30 dB. By the use of a DC operating point control circuit (with external capacitor CAF), the AF preamplifier is decoupled from the PLL DC voltage. The low-pass characteristic of the amplifier reduces the harmonics of the 2nd SIF signal at the AF output terminal. For FM sound a switchable de-emphasis network (with external capacitor) is implemented between the preamplifier and the output amplifier. The AF output amplifier provides the required AF output level by a rail-to-rail output stage. A preceding stage makes use of an input selector for switching between FM sound, AM sound and mute state. The gain can be switched between 10 dB (normal) and 4 dB (reduced). Switching to the mute state is controlled automatically, dependent on the digital acquisition help in case the VCO of the FM PLL is not in the required frequency window. This is done by a time constant: fast for switching to the mute state and slow (typically 40 ms) for switching to the no-mute state. All switching functions are controlled via the I2C-bus: * * * * AM sound, FM sound and forced mute Auto mute enable or disable De-emphasis off or on with 50 s or 75 s Audio gain normal or reduced 8.15 Internal voltage stabilizer The band gap circuit internally generates a voltage of approximately 2.4 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. 8.16 I2C-bus transceiver and MAD The device can be controlled via the 2-wire I2C-bus by a microcontroller. Two wires carry serial data (SDA) and serial clock (SCL) information between the devices connected to the I2C-bus. The device has an I2C-bus slave transceiver with auto-increment. The circuit operates up to clock frequencies of 400 kHz. A slave address is sent from the master to the slave receiver. To avoid conflicts in a real application with other devices providing similar or complementing functions, there are four possible slave addresses available. These MADs can be selected by connecting resistors on pin SIOMAD and/or pins SIF1 and SIF2 (see Figure 26). Pin SIOMAD relates with bit A0 and pins SIF1 and SIF2 relate with bit A3. The slave addresses of this device are given in Table 4. The power-on preset value is dependent on the use of pin SIOMAD and can be chosen for 45.75 MHz NTSC as default (pin SIOMAD left open-circuit) or 58.75 MHz NTSC (resistor on pin SIOMAD). In this way the device can be used without the I2C-bus as an NTSC only device. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 13 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Remark: In case of using the device without the I2C-bus, then the rise time of the supply voltage after switching on power must be longer than 1.2 s. Table 4. Slave address detection Selectable address bit A3 MAD1 MAD2 MAD3 MAD4 0 0 1 1 A0 1 0 1 0 Resistor on pin SIF1 and SIF2 no no yes yes SIOMAD no yes no yes Slave address 9. I2C-bus control 9.1 Read format S BYTE 1 A6 to A0 slave address R/W 1 A BYTE 2 D7 to D0 data NA P from master to slave from slave to master S = START condition A = acknowledge NA = not acknowledge P = STOP condition 008aaa115 Fig 5. I2C-bus read format (slave transmits data) The master generates an acknowledge when it has received the data word READ. The master next generates an acknowledge, then slave begins transmitting the data word READ, and so on until the master generates an acknowledge-not bit and transmits a STOP condition. 9.1.1 Slave address The first module address MAD1 is the standard address (see Table 4). Table 5. Slave addresses For MAD activation via external resistor: see Table 4 and Figure 26. For applications without I2C-bus: see Table 16 and Table 17. Slave address Name MAD1 MAD2 MAD3 MAD4 Value 43h 42h 4Bh 4Ah Bit A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 1 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 0 1 0 TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 14 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 9.1.2 Data byte Table 6. MSB D7 AFCWIN Table 7. Bit 7 D6 VIFLEV D5 D4 D3 AFC3 D2 AFC2 D1 AFC1 CARRDET AFC4 Data read register (status register) LSB D0 PONR Description of status register bits Symbol AFCWIN Description AFC window 1 = VCO in 1.6 MHz AFC window[1] 0 = VCO out of 1.6 MHz AFC window 6 VIFLEV VIF input level 1 = high level; VIF input voltage 200 V (typically) 0 = low level 5 CARRDET FM carrier detection 1 = detection 0 = no detection 4 to 1 0 AFC[4:1] PONR automatic frequency control; see Table 8 power-on reset 1 = after power-on reset or after supply breakdown 0 = after a successful reading of the status register [1] If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behavior. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 15 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 8. Automatic frequency control bits f0 is the nominal frequency of fVIF. Bit AFC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AFC3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 AFC2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 AFC1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (f0 - 187.5 kHz) f0 - 162.5 kHz f0 - 137.5 kHz f0 - 112.5 kHz f0 - 87.5 kHz f0 - 62.5 kHz f0 - 37.5 kHz f0 - 12.5 kHz f0 + 12.5 kHz f0 + 37.5 kHz f0 + 62.5 kHz f0 + 87.5 kHz f0 + 112.5 kHz f0 + 137.5 kHz f0 + 162.5 kHz (f0 + 187.5 kHz) fVIF 9.2 Write format S BYTE 1 A6 to A0 slave address R/W 0 A BYTE 2 A7 to A0 subaddress A BYTE 3 bits 7 to 0 data 1 A BYTE n bits 7 to 0 data n A P from master to slave S = START condition A = acknowledge P = STOP condition 001aad166 from slave to master Fig 6. I2C-bus write format (slave receives data) TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 16 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 9.2.1 Subaddress (A data) If more than one data byte is transmitted, then auto-increment is performed: starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 9. Table 9. Definition of the subaddress (second byte after slave address) X = don't care. Register MSB A7[1] SAD for switching mode 0 SAD for adjust mode SAD for data mode [1] [2] LSB A6[2] X X X A5[2] X X X A4[2] X X X A3[2] X X X A2[2] X X X A1 0 0 1 A0 0 1 0 0 0 Bit A7 = 1 is not allowed. Bits A6 to A2 will be ignored by the internal hardware. 9.2.2 Data byte for switching mode (B data) Table 10. Bit 7 Bit description of SAD register for switching mode (SAD = 00) Symbol B7 Description output port 2 for SAW switching or monitoring 1 = high-impedance, disabled or HIGH 0 = low-impedance, active or LOW 6 B6 output port 1 for SAW switching or external input 1 = high-impedance, disabled or HIGH 0 = low-impedance, active or LOW 5 B5 forced audio mute 1 = on 0 = off 4 and 3 B[4:3] TV standard modulation 00 = positive AM TV[1] 01 = not used 10 = negative FM TV 11 = not used 2 B2 carrier mode 1 = QSS mode 0 = intercarrier mode 1 B1 auto mute of FM AF output 1 = active 0 = inactive 0 B0 video mode (sound trap) 1 = sound trap bypass 0 = sound trap active [1] For positive AM TV choose 6.5 MHz for the second SIF. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 17 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 9.2.3 Data byte for adjust mode (C data) Table 11. Bit 7 Bit description of SAD register for adjust mode (SAD = 01) Symbol C7 Description audio gain 1 = -6 dB 0 = 0 dB 6 C6 de-emphasis time constant 1 = 50 s 0 = 75 s 5 C5 de-emphasis 1 = on 0 = off 4 to 0 Table 12. Bit C4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 TDA9885_TDA9886_3 C[4:0] tuner TOP adjustment; see Table 12 Tuner takeover point adjustment bits TOP adjustment (dB) C3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 C2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 C1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0[1] -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 18 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Tuner takeover point adjustment bits ...continued TOP adjustment (dB) C3 0 0 0 0 0 0 C2 1 1 0 0 0 0 C1 0 0 1 1 0 0 C0 1 0 1 0 1 0 -11 -12 -13 -14 -15 -16 Table 12. Bit C4 0 0 0 0 0 0 [1] For 0 dB refer to Section 12 symbol QVTOP. 9.2.4 Data byte for data mode (E data) Table 13. Bit 7 6 Bit description of SAD register for data mode (SAD = 10) Symbol E7 E6 Description VIF AGC and port features; dependent on bit E5; see Table 14 L standard PLL gating 1 = gating in case of 36 % positive modulation 0 = gating in case of 0 % positive modulation 5 4 to 2 1 and 0 E5 E[4:2] E[1:0] VIF, SIF and tuner minimum gain; dependent on bit E7; see Table 14 vision intermediate frequency selection; see Table 15 sound intercarrier frequency selection (sound 2nd IF) 00 = fFM = 4.5 MHz 01 = fFM = 5.5 MHz 10 = fFM = 6.0 MHz 11 = fFM = 6.5 MHz[1] [1] For positive modulation choose 6.5 MHz. Table 14. Function Pin OP1 Pin OP2 Gain [1] Options in extended TV mode; bit B3 = 0 of SAD 00 register Bit E7 = 0 Bit E5 = 0 port function port function normal gain Bit E5 = 1 port function port function minimum gain Bit E7 = 1 Bit E5 = 0 port function VIF-AGC output[1] normal gain Bit E5 = 1 VIF-AGC external input[1] port function external gain The corresponding port function has to be disabled (set to `high-impedance'); see Table 10 and Table note 12 of Table 20. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 19 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators TV standard selection for VIF fVIF (MHz) E3 0 0 1 1 0 0 1 1 E2 0 1 0 1 0 1 0 1 58.75[1] 45.75[1] 38.9 38.0 33.9 33.4 not applicable not applicable Table 15. E4 0 0 0 0 1 1 1 1 [1] Video IF select bits Pin SIOMAD can be used for the selection of the different NTSC standards without I2C-bus. With a resistor on pin SIOMAD, fVIF = 58.75 MHz; without a resistor on pin SIOMAD, fVIF = 45.75 MHz (NTSC-M). Table 16. Register Data setting after power-on reset (default setting with a resistor on pin SIOMAD) Byte MSB 7 6 1 0 0 5 0 1 0 4 1 1 0 3 0 0 0 2 1 0 0 1 1 0 0 LSB 0 0 0 0 Switching mode (B data) 1 Adjust mode (C data) Data mode (E data) Table 17. Register 0 0 Data setting after power-on reset (default setting without a resistor on pin SIOMAD) Byte MSB 7 6 1 0 0 5 0 1 0 4 1 1 0 3 0 0 0 2 1 0 1 1 1 0 0 LSB 0 0 0 0 Switching mode (B data) 1 Adjust mode (C data) Data mode (E data) 0 0 TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 20 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 10. Limiting values Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VP Vn supply voltage voltage on pins VIF1, VIF2, SIF1, SIF2, OP1, OP2, VP and FMPLL pin TAGC tsc Tstg Tamb short-circuit time storage temperature ambient temperature TDA9885T (SO24), TDA9885TS (SSOP24), TDA9886T (SO24) and TDA9886TS (SSOP24) TDA9885HN (HVQFN32) and TDA9886HN (HVQFN32) Vesd electrostatic discharge voltage machine model human body model [1] [2] Class C according to EIA/JESD22-A115. Class 2 according to JESD22-A114. [1] [2] Conditions Min 0 0 Max 5.5 VP 8.8 10 +150 +70 Unit V V V s C C to ground or VP -25 -20 -20 -400 +85 +400 C V -4000 +3500 V 11. Thermal characteristics Table 19. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA9885T (SO24) TDA9885TS (SSOP24) TDA9885HN (HVQFN32) TDA9886T (SO24) TDA9886TS (SSOP24) TDA9886HN (HVQFN32) Conditions in free air 76 118 40 76 118 40 K/W K/W K/W K/W K/W K/W Typ Unit TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 21 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 12. Characteristics Table 20. Characteristics VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol Supply; pin VP VP IP Ptot Power-on reset VP(start) VP(stop) supply voltage for start of reset supply voltage for end of reset decreasing supply voltage increasing supply voltage; I2C-bus transmission enable 2.5 3.0 3.5 4.4 V V supply voltage supply current total power dissipation [1] Parameter Conditions Min 4.5 52 - Typ 5.0 63 305 Max 5.5 70 385 Unit V mA mW P time constant (R x C) for network for applications without at pin VP I2C-bus VIF input voltage sensitivity (RMS value) maximum input voltage (RMS value) overload input voltage (RMS value) internal IF amplitude difference between picture and sound carrier control range VIF gain lower limit -3 dB VIF bandwidth upper limit -3 dB VIF bandwidth differential input resistance differential input capacitance DC input voltage demodulator[4] maximum oscillator frequency for f = 2fPC carrier regeneration vision carrier operating frequencies see Table 13 [3] [3] 1.2 - - s VIF amplifier; pins VIF1 and VIF2 Vi(VIF)(rms) Vi(max)(rms) Vi(ovl)(rms) VIF(int) -1 dB video at output +1 dB video at output [2] 150 - 60 190 0.7 100 440 - V mV mV dB within AGC range; f = 5.5 MHz see Figure 9 GVIF(cr) BVIF(-3dB)(ll) BVIF(-3dB)(ul) Ri(dif) Ci(dif) VI fVCO(max) fVIF 60 120 - 66 15 80 2 3 1.93 140 33.4 33.9 38.0 38.9 45.75 58.75 2.3 - dB MHz MHz k pF V MHz MHz MHz MHz MHz MHz MHz MHz FPLL and true synchronous video fVIF VIF frequency window of digital acquisition help related to fVIF; see Figure 12 - TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 22 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol tacq Vi(lock)(rms) Parameter acquisition time Conditions BL = 70 kHz [5] Min - Typ 30 Max 30 70 Unit ms V input voltage sensitivity for PLL to measured on pins VIF1 be locked (RMS value) and VIF2; maximum IF gain digital acquisition help cycle time VIF VCO steepness VIF phase detector steepness definition: fVIF / VVPLL definition: IVPLL / VIF Tcy(dah) KO(VIF) KD(VIF) - 64 20 23 - s MHz/V A/rad Video output 2 V; pin CVBS Normal mode (sound carrier trap active) and sound carrier on Vo(v)(p-p) Vo V/S Vsync Vclip(u) Vclip(l) Ro Ibias(int) Isink(o)(max) Isource(o)(max) Vo(CVBS) Vo(bl) Vo(bl)(v) Gdif video output voltage (peak-to-peak value) video output voltage difference ratio between video (black-to-white) and sync level sync voltage level upper video clipping voltage level lower video clipping voltage level output resistance internal bias current (DC) maximum output sink current maximum output source current for emitter-follower AC and DC AC and DC 30 dB gain control black level tilt vertical black level tilt for worst case in L standard differential gain negative modulation vision carrier modulated by test line (VITS) only [3] see Figure 7 difference between L and B/G standard 1.7 -12 1.90 1.0 1.5 1 3.9 [6] 2.0 2.33 1.2 0.7 2.0 - 2.3 +12 3.00 1.4 0.9 30 0.5 0.1 1 3 V % V V V mA mA mA dB dB % % VP - 1.1 VP - 1 deviation of CVBS output voltage 50 dB gain control "ITU-T J.63 line 330" B/G standard L standard [7] 2 59 5 7 4 - % % deg dB dif S/NW differential phase weighted signal-to-noise ratio "ITU-T J.63 line 330" unified weighting filter ("ITU-T J.61"); see Figure 13 see Figure 14 f = 1.1 MHz f = 3.3 MHz 56 S/NUW IM(blue) unweighted signal-to-noise ratio intermodulation attenuation at `blue' [7] [8] 47 58 58 51 64 64 - dB dB dB TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 23 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol IM(yellow) Parameter intermodulation attenuation at `yellow' Conditions see Figure 14 f = 1.1 MHz f = 3.3 MHz Vr(PC)(rms) funw(p-p) residual picture carrier (RMS value) robustness for unwanted frequency deviation of picture carrier (peak-to-peak value) robustness for modulator imbalance suppression of video signal harmonics suppression of spurious elements power supply ripple rejection on pin CVBS fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 8 ftrap = 4.5 MHz f = 4.5 MHz f = 4.5 MHz f = 4.724 MHz f = 4.724 MHz f = 3.58 MHz; see Figure 16 ftrap = 5.5 MHz f = 5.5 MHz f = 5.5 MHz f = 5.742 MHz f = 5.742 MHz f = 4.43 MHz; see Figure 18 [11] [11] [8] Min 60 59 [3] Typ 66 65 2 - Max 5 12 Unit dB dB mV kHz fundamental wave and harmonics 3 % residual carrier; 50 % serration pulses; L standard 0 % residual carrier; 50 % serration pulses; L standard; L-gating = 0 % AC load: CL < 20 pF, RL > 1 k - [3] - - 3 % H spur PSRRCVBS [9] 35 40 20 40 25 - dB dB dB [10] M/N standard including Korea; see Figure 15 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency 3.95 30 21 21 15 110 4.05 36 27 27 21 180 250 MHz dB dB dB dB ns B/G standard; see Figure 17 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) 4.90 30 24 21 15 110 5.00 36 30 27 21 180 250 MHz dB dB dB dB ns TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 24 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) Parameter -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency Conditions ftrap = 6.0 MHz f = 6.0 MHz f = 6.0 MHz f = 6.55 MHz f = 6.55 MHz f = 4.43 MHz [11] Min 5.40 26 20 12 10 - Typ 5.50 32 26 18 15 90 Max 160 Unit MHz dB dB dB dB ns I standard; see Figure 19 D/K standard; see Figure 20 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) ftrap = 6.5 MHz f = 6.5 MHz f = 6.5 MHz f = 6.742 MHz f = 6.742 MHz f = 4.28 MHz [11] 5.50 26 20 18 13 - 5.95 32 26 24 18 60 130 MHz dB dB dB dB ns Video output 1.1 V; pin CVBS Trap bypass mode and sound carrier off[12] Vo(v)(p-p) Vsync Vclip(u) Vclip(l) Bv(-1dB) Bv(-3dB) S/NW video output voltage (peak-to-peak value) sync voltage level upper video clipping voltage level lower video clipping voltage level -1 dB video bandwidth -3 dB video bandwidth weighted signal-to-noise ratio AC load: CL < 20 pF, RL > 1 k AC load: CL < 20 pF, RL > 1 k unified weighting filter ("ITU-T J.61"); see Figure 13 [7] see Figure 7 0.95 1.35 3.5 5 7 56 1.10 1.5 3.6 0.9 6 8 59 1.25 1.6 1.0 - V V V V MHz MHz dB S/NUW unweighted signal-to-noise ratio [7] 48 52 - dB TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 25 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol VIF AGC[13] AGC response time to an increasing VIF step AGC response time to a decreasing VIF step negative modulation; 20 dB positive modulation; 20 dB negative modulation; 20 dB positive modulation; 20 dB L standard; fast mode L standard; normal mode Vi(VIF) VVAGC CRstps Vth(VIF) Pin VAGC Ich(max) Ich(add) maximum charge current additional charge current L standard L standard: in the event of missing VITS pulses and no white video content L standard; normal mode L standard; fast mode Tuner AGC; pin TAGC; see Figure 9 to Figure 11 Vi(VIF)(start1)(rms) VIF input signal voltage for minimum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) Vi(VIF)(start2)(rms) VIF input signal voltage for maximum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) QVTOP tuner takeover point accuracy ITAGC = 120 A; RTOP = 22 k or no RTOP and -15 dB via I2C-bus (see Table 12) ITAGC = 120 A; RTOP = 0 or no RTOP and +15 dB via I2C-bus (see Table 12) ITAGC = 120 A; RTOP = 10 k or no RTOP and 0 dB via I2C-bus (see Table 12) ITAGC = 120 A from external source ITAGC = 450 A no tuner gain reduction; VTAGC = 8.8 V maximum tuner gain reduction; VTAGC = 1 V TDA9885_TDA9886_3 Parameter Conditions [14] [14] [14] [14] Min [14] Typ 4 2.6 3 890 2.6 143 -6 -80 200 Max -10 3.5 320 Unit ms ms ms ms ms/dB ms/dB dB V dB/V V tresp(inc) tresp(dec) -2 0.8 120 VIF amplitude step for activating AGC fast mode gain control voltage range control steepness threshold voltage for high level VIF input L standard see Figure 9 definition: GVIF / VVAGC; VVAGC = 2 V to 3 V see Table 6 and Table 7 - 100 100 - A nA Idch discharge current - 35 1.8 2 5 nA A mV 45 90 - mV 7 17 43 mV QVTOP/T Vo Vsat Isink takeover point variation with temperature permissible output voltage saturation voltage sink current 450 0.03 600 0.07 8.8 0.5 0.75 750 dB/K V V A A (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 26 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol GIF Parameter IF slip by automatic gain control Conditions tuner gain current from 20 % to 80 % Min 3 Typ 5 Max 8 Unit dB AFC circuit; pin AFC[15][16]; see Figure 12 Vsat(ul) Vsat(ll) Isource(o) Isink(o) AFCstps QfVIF(a) QfVIF(d) upper limit saturation voltage lower limit saturation voltage output source current output sink current AFC control steepness analog accuracy of AFC circuit definition: IAFC / fVIF IAFC = 0 A; fREF = 4 MHz VP - 0.6 VP - 0.3 160 160 0.85 -20 0.3 200 200 1.05 0.6 240 240 1.25 +20 V V A A A/kHz kHz digital accuracy of AFC circuit via IAFC = 0 A; fREF = 4 MHz; I2C-bus 1 digit = 25 kHz SIF input voltage sensitivity (RMS value) FM mode; -3 dB at intercarrier output pin SIOMAD AM mode; -3 dB at AF output pin AUD -20 - 1 digit 30 +20 kHz + 1 digit 70 V SIF amplifier; pins SIF1 and SIF2 Vi(SIF)(rms) 50 70 70 100 - V mV Vi(max)(rms) maximum input voltage (RMS value) FM mode; +1 dB at intercarrier output pin SIOMAD AM mode; +1 dB at AF output pin AUD 80 [2] 140 66 15 80 2 3 1.93 320 - mV mV dB MHz MHz k pF V Vi(ovl)(rms) GSIF(cr) BSIF(-3dB)(ll) BSIF(-3dB)(ul) Ri(dif) Ci(dif) VI tresp overload input voltage (RMS value) SIF gain control range lower limit -3 dB SIF bandwidth upper limit -3 dB SIF bandwidth differential input resistance differential input capacitance DC input voltage AGC response time to an FM or AM fast step increasing or decreasing SIF step increasing of 20 dB decreasing AM slow step increasing decreasing FM and AM mode; see Figure 11 60 - [3] [3] - SIF-AGC detector 8 25 80 250 ms ms ms ms TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 27 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol Vo(intc)(rms) Parameter IF intercarrier output level (RMS value) Conditions QSS mode; SC1; SC2 off L standard; without modulation intercarrier mode; PC / SC1 = 20 dB; SC2 off Bintc(-3dB)(ul) Vr(SC)(rms) upper limit -3 dB intercarrier bandwidth residual sound carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode Vr(PC)(rms) residual picture carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode H Ro VO Ibias(int) Isink(o)(max) Isource(o)(max) Isource(o) suppression of video signal harmonics output resistance DC output voltage internal bias current (DC) maximum output sink current maximum output source current output source current for emitter-follower AC AC DC; MAD2 activated [18] [17] Min 90 90 12 Typ 140 140 75 15 Max 180 180 - Unit mV mV mV MHz Single reference QSS intercarrier mixer; pin SIOMAD - 2 2 5 5 mV mV 35 [3] 2 5 40 2 1.15 0.8 0.8 0.93 5 20 30 1.20 mV mV dB V mA mA mA mA intercarrier mode; fvideo = 5 MHz 0.90 0.6 0.6 0.75 FM-PLL demodulator[16][19][20][21][22][23] Sound intercarrier output; pin SIOMAD VFM(rms) IF intercarrier level for gain controlled operation of FM PLL (RMS value) IF intercarrier level for lock-in of PLL (RMS value) IF intercarrier level for FM carrier detect (RMS value) sound intercarrier operating FM frequencies see Table 7 see Table 13 [24] corresponding PC / SC ratio at input pins VIF1 and VIF2 is 7 dB to 47 dB 3.2 - 320 mV VFM(lock)(rms) VFM(det)(rms) fFM - 4.5 5.5 6.0 6.5 2 2.3 - mV mV MHz MHz MHz MHz TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 28 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol Vo(AF)(rms) Parameter AF output voltage (RMS value) Conditions 25 kHz FM deviation; 75 s de-emphasis 27 kHz FM deviation; 50 s de-emphasis Vo(AF)(cl)(rms) Vo(AF)/T THD fAF AF output clipping level (RMS value) AF output voltage variation with temperature total harmonic distortion frequency deviation 25 kHz FM deviation; 50 s de-emphasis THD < 1.5 % -6 dB AF output via I2C-bus BAF(-3dB) -3 dB AF bandwidth without de-emphasis; measured with FM-PLL filter of Figure 26 FM PLL only; 27 kHz FM deviation; 50 s de-emphasis black picture; see Figure 21 Vr(SC)(rms) residual sound carrier (RMS value) AM suppression of FM demodulator fundamental wave and harmonics; without de-emphasis referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Figure 8 [20] [20] Min 400 430 1.3 80 Typ 500 540 1.4 Max 600 650 - Unit mV mV V Audio output; pin AUD THD < 1.5 % 3 x 10-3 7 x 10-3 dB/K 0.15 100 0.50 55 110 % kHz kHz kHz S/NW(AF) weighted signal-to-noise ratio of audio signal 52 56 - dB 50 - 56 - 2 dB mV AM(sup) 40 46 - dB PSRRFM Vloop Isource(o)PD(max) Isink(o)PD(max) Isource(o)(dah) Isink(o)(dah) tw(dah) Tcy(dah) TDA9885_TDA9886_3 power supply ripple rejection DC loop voltage maximum phase detector output source current maximum phase detector output sink current digital acquisition help output source current digital acquisition help output sink current digital acquisition help pulse width digital acquisition help cycle time 14 1.5 [24] 20 60 60 55 55 16 64 3.3 - dB V A A A A s s FM-PLL filter; pin FMPLL - [24] [24] [24] (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 29 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol KO(FM) KD(FM) Audio amplifier De-emphasis network; pin DEEM Ro output resistance 50 s de-emphasis; see Table 11 75 s de-emphasis; see Table 11 VAF(rms) VO Vdec IL Ich(max) Idch(max) Ro VO(AUD) RL RL(DC) CL BAF(-3dB)(ul) BAF(-3dB)(ll) mute Vjump audio signal (RMS value) DC output voltage decoupling voltage (DC) leakage current maximum charge current maximum discharge current output resistance DC output voltage load resistance DC load resistance load capacitance upper limit -3 dB AF bandwidth of audio amplifier lower limit -3 dB AF bandwidth of audio amplifier mute attenuation of AF signal DC jump voltage for switching AF output to mute state or vice versa via I2C-bus activated by digital acquisition help or via I2C-bus mute [21] [3] Parameter VCO steepness phase detector steepness Conditions definition: fFM / VFMPLL definition: IFMPLL / FM Min - Typ 3.3 4 Max - Unit MHz/V A/rad 4.4 6.6 - 5.0 7.5 170 2.37 1.50 1.50 2.37 75 50 5.6 8.4 3.3 25 1.85 1.85 300 1.5 20 150 k k mV V V nA A A V k k nF kHz Hz dB mV fAF = 400 Hz; VAUD = 500 mV AF decoupling; pin AFD dependent on fFM intercarrier frequency VO(AUD) < 50 mV 1.5 1.15 1.15 AC-coupled 10 100 150 70 - Audio output; pin AUD TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 30 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol FM Parameter Conditions Min Typ Max Unit operation[22][25] weighted signal-to-noise ratio PC / SC ratio is 21 dB to 27 dB at pins VIF1 and VIF2 black picture white picture 6 kHz sine wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz Single reference QSS AF performance[27][28] S/NW(SC1) weighted signal-to-noise ratio for SC1 PC / SC1 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz 40 dB 50 45 40 56 51 46 dB dB dB Intercarrier AF performance[26] S/NW 35 40 - dB 53 50 44 58 53 48 - dB dB dB 40 45 - dB 45 51 - dB 46 52 - dB TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 31 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol S/NW(SC2) Parameter weighted signal-to-noise ratio for SC2 Conditions PC / SC2 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz AM operation L standard; pin AUD[29]; see Figure 22 and Figure 23 Vo(AF)(rms) THD BAF(-3dB) S/NW(AF) VO(AUD) PSRRAM VI Ri Rxtal Cx fref fref Vref(rms) Ro(ref) CK TDA9885_TDA9886_3 Min 40 Typ - Max - Unit dB 48 46 42 55 51 46 - dB dB dB 29 34 - dB 44 50 - dB 45 51 - dB AF output voltage (RMS value) total harmonic distortion -3 dB AF bandwidth weighted signal-to-noise ratio of audio signal DC potential voltage power supply ripple rejection DC input voltage input resistance resonance resistance of crystal pull-up/down capacitance reference signal frequency tolerance of reference signal frequency reference signal voltage (RMS value) output resistance of reference signal source decoupling capacitance to external reference signal source 54 % AM modulation 54 % AM modulation in accordance with "ITU-R BS.468-4" see Figure 8 400 100 45 20 2.3 [3] 500 0.5 125 50 2.37 26 2.6 5 4 100 600 1.0 2.9 200 0.1 400 4.7 - mV % kHz dB V dB V k pF MHz % mV k pF Reference frequency input; pin REF [30] [31] [16] operation as crystal oscillator 80 - operation as input terminal operation as input terminal 22 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 32 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 20. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 22 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC / SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 26; unless otherwise specified. Symbol I2C-bus fSCL VIH VIL IIH IIL VOL Isink(o) Isource(o) VOL VOH Isink(o) Io(max) Parameter transceiver; pins SDA and SCL[32][33] 0 3 -0.3 -10 -10 IOL = 3 mA VP = 0 V VP = 0 V IOL = 2 mA (sink current) sink or source; pin OP2 functions as VIF-AGC output 400 VCC +1.5 +10 +10 0.4 10 10 0.4 6 2 10 kHz V V A A V A A V V mA A SCL clock frequency HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage output sink current output source current OP2[34] LOW-level output voltage HIGH-level output voltage output sink current maximum output current Conditions Min Typ Max Unit Output ports; pins OP1 and [1] [2] [3] [4] Values of video and sound parameters can be decreased at VP = 4.5 V. Level headroom for input level jumps during gain control setting. This parameter is not tested during the production and is only given as application information for designing the receiver circuit. Loop bandwidth BL = 70 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF-PLL filter can be done by use of the following formula: 1 BL - 3dB = ----- O K D R , valid for d 1.2 -K 2 1 d = -- R K O K D C , 2 where: Hz A rad KO is the VCO steepness ------- or 2 ----- ; KD is the phase detector steepness ------- ; V V rad R is the loop resistor (); C is the loop capacitor (F); BL-3dB is the loop bandwidth for -3 dB (Hz); d is the damping factor. [5] [6] [7] Vi(VIF) = 10 mV (RMS); f = 1 MHz (VCO frequency offset related to the picture carrier frequency); white picture video modulation. Condition: luminance range (5 steps) from 0 % to 100 %. S/N is the ratio of black-to-white amplitude to the noise voltage (RMS value measured on pin CVBS and tested at video black level, `quiet line'). Noise analyzer settings: B = 5 MHz, 200 kHz high-pass and sound carrier trap on. In case of S/NW weighted in accordance with "ITU-T J.61". Measurements taken for B/G standard. The intermodulation figures are defined for: a) f = 1.1 MHz (referenced to black and white signal) as IM = 20 log ------------------------------------- + 3.6 dB V at 1.1 MHz 0 [8] V 0 at 4.4 MHz b) f = 3.3 MHz (referenced to color carrier) as IM = 20 log ------------------------------------- V at 3.3 MHz 0 V 0 at 4.4 MHz TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 33 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators [9] Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. Modulation VSB; sound carrier off; fvideo > 0.5 MHz. [10] Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. Sound carrier on; fvideo = 10 kHz to 10 MHz. [11] AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps (see Figure 15 to Figure 20; H (s) is the absolute value of transfer function). [12] The sound carrier trap can be bypassed by switching the I2C-bus. In this way the full composite video spectrum appears at pin CVBS. The amplitude is 1.1 V (p-p). [13] If selected by the I2C-bus, the VIF-AGC voltage can be monitored at pin OP2, and pin OP1 can be used as input. In this case, both pins cannot be used for the normal port function. [14] The response time is valid for a VIF input level range from 200 V to 70 mV. [15] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 12. The AFC slope (voltage per frequency) can be changed by resistors R1 and R2. [16] The tolerance of the reference frequency determines the accuracy of the VIF AFC, FM demodulator center frequency and maximum FM deviation. [17] The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: V o(intc)(rms) = 1.1 x --------- x 10 V and r = ----- x --------------- ( dB ) + 6 dB 3 dB , where: --------- is the 20 V i ( PC ) 22 22 1 r 1 V i ( SC ) 1 correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 in dB, 6 dB is the correction term of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). [18] For normal operation (with the I2C-bus) no DC load at pin SIOMAD is allowed. The second module address (MAD2) will be activated by the application of a 2.2 k resistor between pin SIOMAD and ground. If this MAD2 is activated, also the power-on set-up state activates a VIF frequency of 58.75 MHz. [19] SIF input level is 10 mV (RMS); VIF input level is 10 mV (RMS) unmodulated. [20] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The AF output signal can be attenuated by 6 dB to 250 mV (RMS) via the I2C-bus. For handling a frequency deviation of more than 55 kHz, the AF output signal has to be reduced in order to avoid clipping (THD < 1.5 %). [21] The lower limit of the audio bandwidth depends on the value of the capacitor at pin AFD. A value of CAF = 470 nF leads to fAF(-3dB) 20 Hz and CAF = 220 nF leads to fAF(-3dB) 40 Hz. [22] For all S/N measurements the VIF modulator in use has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter) [23] Calculation of the loop filter parameters can be done approximately using the following formulae: f o = ----- --------------- ; - V i ( SC ) V i ( PC ) 1 K OK D 2 CP 1 = ---------------------------------- ; BL-3dB = fo(1.55 - 2). The formulae are only valid under the following conditions: 1 and CS > 5CP, where: 2R K O K D C P A Hz rad KO is the VCO steepness -------- or 2 ------ ; KD is the phase detector steepness -------- ; R is the loop resistor; CS is the series V V rad capacitor; CP is the parallel capacitor; fo is the natural frequency of the PLL; BL-3dB is the loop bandwidth for -3 dB; is the damping factor. For examples, see Table 21. [24] Window width of digital acquisition help 237.5 kHz. [25] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is necessary to achieve the S/NW values as noted. A different PC / SC ratio will change these values. [26] Measurements taken with SAW filter G1984 (Siemens) for vision and sound IF (sound shelf: 14 dB). Picture-to-sound carrier ratio of transmitter PC / SC = 13 dB. Input level on pins VIF1 and VIF2 of Vi(SIF) = 10 mV (RMS) sync level, 27 kHz FM deviation for sound carrier, fAF = 400 Hz. Measurements in accordance with "ITU-R BS.468-4". De-emphasis is 50 s. [27] The QSS signal output on pin SIOMAD is analyzed by a test demodulator TDA9820. The S/N ratio of this device is more than 60 dB, related to a deviation of 27 kHz, in accordance with "ITU-R BS.468-4". TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 34 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators [28] Measurements taken with SAW filter K3953 for vision IF (suppressed sound carrier) and K9453 for sound IF (suppressed picture carrier). Input level Vi(SIF) = 10 mV (RMS), 27 kHz (54 % FM deviation). [29] Measurements taken with SAW filter K9453 (Siemens) for AM sound IF (suppressed picture carrier). [30] The value of Cx determines the accuracy of the resonance frequency of the crystal. It depends on the type of crystal used. [31] Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. [32] The SDA and SCL lines will not be pulled down if VCC is switched off. [33] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). [34] Port P1 and port P2 are open-collector outputs. Table 21. 100 160 Table 22. Symbol fPC fSC1 fSC2 Examples to the FM-PLL filter CS (nF) 10 10 Input frequencies and carrier ratios Parameter picture carrier frequency sound carrier frequency 1 sound carrier frequency 2 B/G standard M/N standard L standard L-accent standard Unit 38.9 33.4 33.158 13 20 45.75 or 58.75 38.9 41.25 or 54.25 32.4 7 10 33.9 40.4 10 MHz MHz MHz dB dB CP (pF) 390 150 R (k) 5.6 9.1 0.5 0.5 BL-3dB (kHz) PC / SC1 picture to first sound carrier ratio PC / SC2 picture to second sound carrier ratio trap bypass mode normal mode 2.72 V 2.6 V 3.41 V 3.20 V zero carrier level white level 1.83 V 1.80 V black level 1.5 V 1.20 V sync level mhc115 Fig 7. Typical video signal levels on output pin CVBS (sound carrier off) TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 35 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators VP = 5 V VP (V) 5 100 mV TDA9885 TDA9886 fripple = 70 Hz t (s) mhc114 Fig 8. Ripple rejection condition mhc116 VVAGC (V) 4 I TAGC (A) 600 500 400 3 300 200 2 (1) (2) (3) (4) 100 0 1 30 40 50 60 70 80 90 100 110 120 Vi(VIF) (dBV) (1) VVAGC is VIF-AGC voltage and can only be measured at pin OP2 controlled by the I2C-bus (see Table 14). (2) ITAGC is tuner current in TV mode with RTOP = 22 k or setting via I2C-bus at -15 dB. (3) ITAGC is tuner current in TV mode with RTOP = 10 k or setting via I2C-bus at 0 dB. (4) ITAGC is tuner current in TV mode with RTOP = 0 k or setting via I2C-bus at +15 dB. Fig 9. Typical VIF and tuner AGC characteristic TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 36 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 110 Vi(VIF) (dBV) 100 mhb159 90 80 70 60 0 4 8 12 16 20 24 RTOP (k) Fig 10. Typical tuner takeover point as a function of resistor RTOP 5 VSAGC (V) 4 mhc117 3 (1) (2) 2 1 30 50 70 90 110 130 Vi(SIF) (dBV) (1) FM mode. (2) AM mode. Fig 11. Typical SIF-AGC characteristic TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 37 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators lock range without SAW filter AFC window 5 VP VAFC (V) 4 -100 R1 22 k IAFC (A) -200 3 0 2 +100 1 +200 0 36 37 38 38.9 38.71 39.09 40 f (MHz) mhc113 TDA9885 21 TDA9886 (23) IAFC VAFC R2 22 k 41 Pin numbers for TDA9885HN and TDA9886HN in parentheses. Fig 12. Typical analog AFC characteristic 3.2 dB 80 S/N (dB) 60 mhc112 10 dB 13.2 dB 21 dB 13.2 dB 21 dB 40 SC CC PC SC CC PC BLUE 20 YELLOW mha739 SC is sound carrier, with respect to sync level. CC is chrominance carrier, with respect to sync level. 0 30 PC is picture carrier, with respect to sync level. 50 70 110 90 Vi(VIF) (dBV) The sound carrier level takes into account a sound shelf attenuation of 14 dB (SAW filter G1984M). Fig 13. Typical signal-to-noise ratio as a function of VIF input voltage Fig 14. Input signal conditions TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 38 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 10 H(s) (dB) 0 mhc122 -10 -20 -30 minimum requirements -40 2 2.5 3 3.5 4 4.5 f (MHz) 5 Fig 15. Typical amplitude response for sound trap at M/N standard (including Korea) 400 group delay (ns) 300 mhb167 200 ideal characteristic due to pre-correction in the transmitter 100 0 minimum requirements -100 0 0.5 1 1.5 2 2.5 3 3.5 f (MHz) 4 Overall delay is not shown, here the maximum ripple is specified. Fig 16. Typical group delay for sound trap at M/N standard TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 39 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 10 H(s) (dB) 0 mhb168 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 17. Typical amplitude response for sound trap at B/G standard 400 group delay (ns) 300 mhb169 200 ideal characteristic due to pre-correction in the transmitter 100 0 minimum requirements -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 f (MHz) 5 Overall delay is not shown, here the maximum ripple is specified. Fig 18. Typical group delay for sound trap at B/G standard TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 40 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators mhc123 10 H(s) (dB) 0 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 19. Typical amplitude response for sound trap at I standard mhb171 10 H(s) (dB) 0 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 20. Typical amplitude response for sound trap at D/K standard TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 41 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 10 (1) mhc118 S/NW 0 (dB) -10 -20 -30 -40 (2) -50 -60 -70 (3) 52 49 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 PC/SC ratio gain controlled operation of FM-PLL Conditions: PC / SC ratio measured at pins VIF1 and VIF2; via transformer; 27 kHz FM deviation; 50 s de-emphasis. (1) Signal. (2) Noise at H-picture ("ITU-R BS.468-4" weighted quasi peak). (3) Noise at black picture ("ITU-R BS.468-4" weighted quasi peak). Fig 21. Audio signal-to-noise ratio as a function of picture-to-sound carrier ratio in intercarrier mode 10 S/NW 0 (dB) -10 -20 -30 -40 -50 -60 -70 30 40 50 60 70 80 90 (2) (1) mhc119 100 Vi (dBV) 110 Condition: m = 54 %. (1) Signal. (2) Noise. Fig 22. Typical audio signal-to-noise ratio as a function of input signal at AM standard TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 42 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 1.5 THD (%) 1.0 mhc120 0.5 0 10-2 10-1 1 10 fAF (kHz) 102 CAGC = 2.2 F; m = 54 %. Fig 23. Typical total harmonic distortion as a function of audio frequency at AM standard TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 43 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 140 antenna input (dBV) 10 IF signals RMS value (V) video 2 V (p-p) 1 120 (1) 100 SAW insertion loss 20 dB 10-1 IF slip 6 dB 80 tuning gain control range 70 dB VIF AGC 60 10-2 (TOP) 10-3 0.66 x 10-3 SAW insertion loss 20 dB 40 40 dB RF gain 10-4 20 10-5 0.66 x 10-5 10 VHF/UHF tuner tuner VIF SAW filter VIF amplifier, demodulator and video TDA9885, TDA9886 mhc121 (1) Depends on TOP. Fig 24. Front-end level diagram TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 44 of 56 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 03 -- 16 December 2008 (c) NXP B.V. 2008. All rights reserved. TDA9885_TDA9886_3 13. Application information NXP Semiconductors 5V 3.9 k 4.7 k CVBS output fref tuner AGC (4) (5) 10 F 10 nF 75 12 k 1 2 SAW FILTER K9650 3 5 4 1 nF 1.5 nF 330 220 BC847B 3.3 pF 100 k 47 F (5) (5) 5V 3.9 k BA277 BA277 5V 10 nF 220 nF 470 nF 100 pF 4.7 k 10 nF SIF2 24 (27) SIF1 23 (26) OP2(1)(2) 22 (24) AFC 21 (23) VP 20 (22) VPLL 19 (21) AGND 18 (20) CVBS 17 (18) VAGC(3) 16 REF 15 (16) TAGC 14 (15) n.c. 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) I2C-bus controlled multistandard alignment-free IF-PLL demodulators OP1(1) TDA9885 TDA9886 (30) 1 VIF1 IF input (6) (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5 DEEM (4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA 100 (10) 11 SCL 100 (11) 12 SIOMAD 1 51 5 SAW FILTER K3953 3 4 390 pF 10 nF 10 nF 470 nF 10 nF 2 5.6 k (4) AF output positive supply I2C-bus controller I2C-bus intercarrier output 008aaa175 TDA9885; TDA9886 Pin numbers for TDA9885HN and TDA9886HN in parentheses. (1) For L-accent standard OP1 = LOW and OP2 = HIGH, in other cases OP1 = HIGH and OP2 = LOW. (2) If pin OP2 outputs VIF-AGC voltage, then pin OP1 can be used for SAW switching. (3) Not connected for TDA9885. (4) Optional measures to improve ESD performance within a TV-set application. (5) Application dependent. (6) For test signal input only. 45 of 56 Fig 25. Application diagram xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 03 -- 16 December 2008 (c) NXP B.V. 2008. All rights reserved. TDA9885_TDA9886_3 14. Test information NXP Semiconductors SIF input AFC output 1:1 22 k 100 nF VP 1.5 nF VIF-PLL filter (2) CVBS output external reference tuner AGC output 150 100 pF 4 MHz Cx 51 R3 150 k (1) R2 150 k 22 k 220 nF 470 nF SIF2 24 (27) SIF1 23 (26) OP2 22 (24) AFC 21 (23) VP 20 (22) VPLL 19 (21) AGND 18 (20) CVBS 17 (18) VAGC(3) 16 REF 15 (16) TAGC 14 (15) n.c. I2C-bus controlled multistandard alignment-free IF-PLL demodulators TDA9885 TDA9886 (30) 1 VIF1 VIF input (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5 DEEM (4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA (10) 11 SCL 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) (11) 12 SIOMAD 1:1 10 nF 390 pF 10 nF 470 nF 22 k R1 2.2 k (1) 51 5.6 k MAD select TDA9885; TDA9886 FM-PLL filter audio output intercarrier output mhc124 Pin numbers for TDA9885HN and TDA9886HN in parentheses. (1) Optional for I2C-bus address selection; see Table 23. (2) Different VIF loop filter in comparison with the application diagram due to different input characteristics (SAW filter or transformer). (3) Not connected for TDA9885. 46 of 56 Fig 26. Test circuit NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Table 23. I2C-bus address selection S = R/W selection bit. Option R2 and R3 not used R2 = R3 = 150 k R1 not used 1000 011S 1001 011S R1 = 2.2 k 1000 010S 1001 010S TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 47 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 15. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 27. Package outline SOT137-1 (SO24) TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 48 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 28. Package outline SOT340-1 (SSOP24) TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 49 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-3 D B A terminal 1 index area A E A1 c detail X C e1 e 9 L 8 17 e 1/2 e b 16 vMCAB wM C y1 C y Eh 1/2 e e2 1 terminal 1 index area 32 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.75 3.45 E (1) 5.1 4.9 Eh 3.75 3.45 25 24 X 2.5 scale e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 5 mm v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-04-18 02-10-22 Fig 29. Package outline SOT617-3 (HVQFN32) TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 50 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 51 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24 and 25 Table 24. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 25. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 52 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. Abbreviations Table 26. Acronym AF AFC AGC DSB FPLL IF MAD NTSC PAL PC PC PLL QSS SAD SAW SC SECAM SIF STB TDA9885_TDA9886_3 Abbreviations Description Audio Frequency Automatic Frequency Control Automatic Gain Control Double SideBand Frequency Phase-Locked Loop Intermediate Frequency Module ADdress National Television Standards Committee Phase Alternating Line Personal Computer Picture Carrier Phase-Locked Loop Quasi Split Sound SubADdress Surface Acoustic Wave Sound Carrier SEquentiel Couleur Avec Memoire Sound Intermediate Frequency Set-Top Box (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 53 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators Abbreviations ...continued Description TakeOver Point Voltage-Controlled Oscillator Vision Intermediate Frequency Vertical Interval Test Signal Video Tape Recorder Table 26. Acronym TOP VCO VIF VITS VTR 18. Revision history Table 27. Revision history Release date 20081216 Data sheet status Product data sheet Change notice Supersedes TDA9885_TDA9886_2 Document ID TDA9885_TDA9886_3 Modifications: * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 5: added V5 versions Figure 25; update on application diagram Product specification Product specification TDA9885_TDA9886_1 - TDA9885_TDA9886_2 TDA9885_TDA9886_1 20031002 20020305 TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 54 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 19.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA9885_TDA9886_3 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 -- 16 December 2008 55 of 56 NXP Semiconductors TDA9885; TDA9886 I2C-bus controlled multistandard alignment-free IF-PLL demodulators 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.2.4 10 11 12 13 14 15 16 16.1 16.2 16.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 8 VIF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Tuner AGC and VIF AGC . . . . . . . . . . . . . . . . . 8 VIF-AGC detector . . . . . . . . . . . . . . . . . . . . . . . 9 FPLL detector . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCO and divider . . . . . . . . . . . . . . . . . . . . . . . . 9 AFC and digital acquisition help . . . . . . . . . . . 10 Video demodulator and amplifier . . . . . . . . . . 10 Sound carrier trap . . . . . . . . . . . . . . . . . . . . . . 11 SIF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SIF-AGC detector . . . . . . . . . . . . . . . . . . . . . . 11 Single reference QSS mixer . . . . . . . . . . . . . . 11 AM demodulator . . . . . . . . . . . . . . . . . . . . . . . 12 FM demodulator and acquisition help. . . . . . . 12 Audio amplifier and mute time constant . . . . . 12 Internal voltage stabilizer . . . . . . . . . . . . . . . . 13 I2C-bus transceiver and MAD . . . . . . . . . . . . . 13 2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 14 I Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Subaddress (A data). . . . . . . . . . . . . . . . . . . . 17 Data byte for switching mode (B data) . . . . . . 17 Data byte for adjust mode (C data). . . . . . . . . 18 Data byte for data mode (E data) . . . . . . . . . . 19 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal characteristics. . . . . . . . . . . . . . . . . . 21 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 22 Application information. . . . . . . . . . . . . . . . . . 45 Test information . . . . . . . . . . . . . . . . . . . . . . . . 46 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48 Soldering of SMD packages . . . . . . . . . . . . . . 51 Introduction to soldering . . . . . . . . . . . . . . . . . 51 Wave and reflow soldering . . . . . . . . . . . . . . . 51 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 51 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 53 54 55 55 55 55 55 55 56 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 December 2008 Document identifier: TDA9885_TDA9886_3 |
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